An Overview Of The Different Types Of LCD Display Interfaces


Freddy Aceves

Sr. Display Solutions Architect



Everywhere we go, whether the airport, retail store or inside our vehicles, LCD displays are a huge part of our everyday life. From providing us with data regarding weather, GPS information or just entertainment, LCD’s are everywhere, but how are these various displays interfaced?

A liquid crystal display module consists of a TFT Cell, Driver IC/Source PCB and a backlight unit. Many displays, usually depending on the size, will use different interface technologies.

Below you will find a general list of typical LCD sizes and common interfaces out in the market today.

  • 2” ~ 5.7” = MIPI-SPI/RGB/MPU
  • 6” ~ 23” = LVDS/eDP
  • 24” ~ 100” = VbyOne/LVDS

In this paper we will provide you with an overview of the different type of interfaces commonly used in today’s LCD product offerings.


Low Voltage Differential Signaling (LVDS)


The first interface we will look at will be Low Voltage Differential Signaling or more commonly known as LVDS. Introduced in 1994, this interface was extremely popular for many years in LCD displays. There are 2 standards that govern LVDS, 1) ANSI/TIA/EIA-644 and 2) IEEE. LVDS has a high-speed capability which can reach Gbps to extend the full physical distance while maintaining signal integrity. Minimized EMI and high noise immunity, skew and low jitter are some benefits. Other benefits from using LVDS are low power, low cost, small footprint and simple implementation. LVDS supports data, clock and control signals. LVDS is activated by 3.5mA constant current along with the transmission of high-speed differential signal data that carries an exceptionally low voltage swing of 350mV terminated with a 100Ω load, see Fig 1.

LVDS Block Diagram
Fig. 1



There are 7-bit data streams (28 bit of data (4 x7=28)) of incoming data streams to the serializer (Tx), converted to LVDS and sent to de-serializer (Rx), see Fig 2. Clock signals are usually sent separately.


LVDS SerDes Block Diagram
Fig 2


Low PowerOlder Technology
Low Cost
High Noise Immunity

Embedded Display Port (eDP)


eDP was first introduced in 2008 as a simplified version of DisplayPort with the intent to replace LVDS for internal displays. Some advantages to using eDP are higher display performance (resolution, refresh rate, color accuracy), integrated support for legacy video adapters, power reduction resulting in increased battery life, easier IC integration reduction of signal wires (compared to LVDS) and decreased interference with wireless services. Currently this technology has been seen on Small to Medium sized displays. Some features are as follows:

1 to 4 data pairs, no separate clock pairs, Bit Rate: 1.6 or 2.7 Gbit/sec, total raw capacity: 1.6 to 10.8 Gbit/sec, embedded clock, full audio support, Aux channel 1Mbps, channel coding: ANSI8B-10B, Protocol: Micro-packed based. Since its inception, this standard has gone through a series of revision updates adding features not shared with DisplayPort. In 2010 eDP version 1.2 was released adding control of display and backlight features over the auxiliary channel. In version 1.3, VESA introduced Panel Self Refresh (PSR) which is an SoC power optimizer in the event the display image becomes static. See below typical eDP functional diagram (Fig.3).

eDP Interface
Fig. 3
Low pin countLCD size limitation
Higher display performanceExpensive interface connector

Mobile Industry Processor Interface - Display Serial Interface (MIPI-DSI)


Developed by the MIPI Alliance, MIPI-DSI is a high-speed serial interface most used on smaller devices like tablets, smartphones, automotive dashboard displays and wearables. This specification defines the interface between the display and processer. DSI also uses the D-PHY specification for control and data transport. Some of the key features from using MIPI are high performance, low power, low EMI and reduced pin count for interface. Data and pixel commands are serialized into one physical stream. DSI used with D-PHY enables the use of all eight lanes which can support realistic color rendering and high-definition images. See below typical MIPI functional diagram. (Fig.4).

MIPI Interface Specification
Fig. 4
Low pin countComplex board design requirement
Low PowerProtocol and driver software req.
Low EMI 




RGB interface is a type of parallel interface. This interface works without a frame buffer and requires the MCU to provide updates to the display. The MCU will be tasked with updating the timing signals (VSYN, HSYNC, DE, CLK) and RGB sub-pixel data (16-bit, 18-bit, 24-bit) manually to the display.

High performanceHigh interface pin count
Bandwidth up to 1.2GB/secSusceptible to electrical noise



V-By-One was created to be the successor to LVDS and is currently being used on a number of LCD modules larger than 42” in size. With displays having higher resolutions and frame rates, V By One was created to address the typical attenuation of signal amplitude and skew problems between signals attributed with cable count. Integrated with its Clock Data Recovery (CDR) and Adaptive equalizer technology, signal conditioning can be achieved at high data speeds over long distance. With V by One, 32 signal lines in 16 pairs will be sufficient for 4K/120Hz images because the data transmission speed per pair is at 4G bit/sec at maximum resulting in one FFC and one connector being used for image/video data transmission.

V-By-One Display Interface
Fig. 5
Higher ResolutionSpecialized FPGA support
Clock Data Recovery 




I2C combines features of SPI and UARTs. It utilizes a multi-master, multi-slave, single ended, pack switched and is a synchronous communication bus. Unlike SPI which uses a slave for data transfer, I2C used addressing frame bit to start a new message. The master sends the start condition to all connected slave by switching the SDA from a high voltage level to a low before switching the SCL line from high to low. Master now sends each slave the 7-to-10-bit address of the slave it wants to communicate with along with read/write bit. Slave compares the address sent from the master to its own address. If the address matches, the slave returns and acknowledgment bit by pulling the SDA line low for the one bit. If master and slave do not match the slave leaves the SDA line high. The master sends or receives the data frame and after each frame has been transferred, the receiving device returns another Ack bit to the sender and acknowledges successful receipt of the frame. In order to stop the data transmission, the master sends a stop condition to the slave by switching SCL high before switching SDA high.

Widely used protocolSlower data transfer than SPI
Only uses 2 wiresData frame limited to 8 bits



SPI or Serial Peripheral Interface is a serial communication interface meant to be used in short distance applications. This interface allows for the microcontroller/microprocessor to connect and communicate with separate controllers and peripheral devices, like LCD’s. Using a master/slave architecture with a single master, SPI communicates in full duplex mode, transmission of data is simultaneous and bi-directional. There are 4 signals that make up SPI:

  • Master Out Slave In (MOSI) – Signal created by the signal generating device like microcontroller/microprocessor and sent to the peripheral device.
  • Master In Slave Out (MISO) – Slave (peripheral device, i.e. LCD controller) generates MISO signals and sends back to the master (microcontroller/microprocessor).
  • Serial Clock (SCLK or SCK) – The serial clock signal is generated by the master and synchronizes data transfers between the master and slave.
  • Slave Select (SS) – This signal is generated by the master. This selects which peripheral is receiving the signal from toe microcontroller/microprocessor. Below figure outlines the basic SPI bus.
SPI Display Interface
Fig. 6
Supports Multiple PeripheralsRequires more signal wires




MCU interface is used to send the LCD controller two types of signals, data and control. Data signals are connected to the LCD data bus and are dependent on the LCD color depth (8-Bit, 16-Bit). Control signals are used to define the operation type, write or read. This controls the operation in addressing LCD registers or display RAM.

SimpleRequires display RAM





Regardless of the interface type you might be trying to develop an LCD solution around, Macnica Displays has the product ready to help with connectivity, ranging from FPGA’s, Embedded Computers or LCD Controller Boards, we are here to help.



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